A capacitor for use in, for example, a circuit for a CPU (Central Processing Unit) in a personal computer and the like is required to have high capacity and low ESR (Equivalent Series Resistance) to control voltage fluctuation and suppress heat generation during the passing of high ripple currents.
As a capacitor for use in a CPU circuit, an aluminum solid electrolytic capacitor and a tantalum solid electrolytic capacitor are known. As such solid electrolytic capacitor, it is known that the capacitor is constituted by one of electrodes (conductive member) made of an aluminum foil having minute pores in a surface layer or a sintered body formed by sintering tantalum powder having minute pores therein, a dielectric layer formed on the surface of the one of the electrodes, and the other electrode (typically, a semiconductor layer) formed on the dielectric layer.
As a forming method of a semiconductor layer of a capacitor in which the semiconductor layer constitutes the other electrode, methods using an energization method described in U.S. Pat. No. 1,868,722 (Patent Document 1), U.S. Pat. No. 1,985,056 (Patent Document 2), and U.S. Pat. No. 2,054,506 (Patent Document 3) are known. In all of the methods, a semiconductor layer is formed by immersing a conductive member having a dielectric layer on the surface thereof into semiconductor layer forming solution and applying voltage (passing electrical current) between the conductive member as an anode and a cathode prepared in the semiconductor layer forming solution.
Japanese Unexamined Laid-open Patent Application Publication No. 1-13-22516 (Patent Document 4) describes a method for forming a semiconductor layer by passing an electric current in which a DC bias current is superimposed on an alternating current through a conductive member having a dielectric layer. Further, Japanese Unexamined Laid-open Patent Application Publication No. H3-163816 (Patent Document 5) describes a method for forming a semiconductor layer on a chemical polymerization layer by having a conductive member come in contact with a chemical polymerization layer formed on the dielectric layer and electropolymerizing using the conductive member as an anode.
However, with the methods as described in Patent Documents 4 and 5, there were the following problems when simultaneously forming a semiconductor layer on each of a plurality of conductive members. That is, with the method described in Patent Document 4, a semiconductor layer is also formed on the cathode side and there is a problem that the formation condition of the semiconductor layer changes as the energizing time passes, and it was also difficult to evenly passing electric current through a plurality of conductive members. Further, with the method described in Patent Document 5, it is difficult to form a uniform semiconductor layer on the inside of each conductive member since energizing is conducted through a conductive member arranged on the outside and used as an anode. In the case of a large conductive member having small pores formed therein, it was especially difficult to form a uniform semiconductor layer.
In cases where a semiconductor layer is formed on the aforementioned conductive member in which a dielectric layer is formed by the energizing method, there were no problems when forming a semiconductor layer on each of a few conductive members. However, in the case of simultaneously forming a semiconductor layer on each of one hundred or more conductive members at an industrial level, since the individual conductive members are not always homogeneous, and the semiconductor forming speeds are different from each other depending on conductive members, especially when a semiconductor layer is formed simultaneously on a plurality of conductive members, the current value of the electricity flowing through each conductive member does not become constant, and it was sometimes difficult to manufacture capacitors having stable capacity since the formation condition of the semiconductor layer of the manufactured capacitor was uneven.
Therefore, the inventors proposed a reaction container having a configuration in which small reaction containers (compartments) corresponding to the individual conductive members were arranged (See Patent Documents 6 and 7).